HD64F3048VTF8 Datasheet, PDF (831/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

TCSR—Timer Control/Status Register
Bit
7
6
5
4
OVF WT/ IT TME

Initial value
0
0
0
1
Read/Write R/(W)* R/W R/W

Appendix B Internal I/O Register
H'A8
WDT
3
2
1
0

CKS2 CKS1 CKS0
1
0
0
0

R/W
R/W
R/W
Timer enable
0 Timer disabled
• TCNT is initialized to H'00 and halted
1 Timer enabled
• TCNT is counting
• CPU interrupt requests are enabled
Timer mode select
0 Interval timer: requests interval timer interrupts
1 Watchdog timer: generates a reset signal
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT changes from H'FF to H'00
Note: * Only 0 can be written, to clear the flag.
Clock select 2 to 0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
Rev. 3.00 Sep 27, 2006 page 803 of 872
REJ09B0325-0300