HD64F3048VTF8 Datasheet, PDF (433/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Read and Input Capture
If an input capture signal occurs during the T₃ state of a general register read cycle, the value
before input capture is read. See figure 10.66.
General register read cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 10.66 Contention between General Register Read and Input Capture
Rev. 3.00 Sep 27, 2006 page 405 of 872
REJ09B0325-0300