HD64F3048VTF8 Datasheet, PDF (114/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 4 Exception Handling
φ
RES
Address bus
RD
HWR, LWR
D₁₅ to D₀
Vector fetch
Internal
processing
Prefetch of first
program instruction
(1)
(3)
(5)
High
(2)
(4)
(6)
(1), (3)
(2), (4)
(5)
(6)
Address of reset vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset vector)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4.3 Reset Sequence (Modes 2 and 4)
Rev. 3.00 Sep 27, 2006 page 86 of 872
REJ09B0325-0300