HD64F3048VTF8 Datasheet, PDF (228/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
8.1.2 Block Diagram
Figure 8.1 shows a DMAC block diagram.
Internal address bus
Internal
interrupts
IMIA0
IMIA1
IMIA2
IMIA3
TXI0
RXI0
DREQ0
DREQ1
TEND0
TEND1
Interrupt
signals
DEND0A
DEND0B
DEND1A
DEND1B
Control logic
DTCR0A
DTCR0B
DTCR1A
DTCR1B
Data buffer
Channel
0
Channel
0A
Channel
0B
Channel
1
Channel
1A
Channel
1B
Address buffer
Arithmetic-logic unit
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
Internal data bus
Legend:
DTCR: Data transfer control register
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Figure 8.1 Block Diagram of DMAC
Rev. 3.00 Sep 27, 2006 page 200 of 872
REJ09B0325-0300