HD64F3048VTF8 Datasheet, PDF (237/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6: DTSZ
0
1
Description
Byte-size transfer
Word-size transfer
(Initial value)
Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or
decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.
Bit 5: DTID
0
1
Description
MAR is incremented after each data transfer
• If DTSZ = 0, MAR is incremented by 1 after each transfer
• If DTSZ = 1, MAR is incremented by 2 after each transfer
MAR is decremented after each data transfer
• If DTSZ = 0, MAR is decremented by 1 after each transfer
• If DTSZ = 1, MAR is decremented by 2 after each transfer
MAR is not incremented or decremented in idle mode.
Bit 4—Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat
mode.
Bit 4: RPE
0
1
Bit 3: DTIE
0
1
0
1
Description
I/O mode
Repeat mode
Idle mode
(Initial value)
Operations in these modes are described in sections 8.4.2, I/O Mode, 8.4.3, Idle Mode, and 8.4.4,
Repeat Mode.
Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3: DTIE
0
1
Description
The DEND interrupt requested by DTE is disabled
The DEND interrupt requested by DTE is enabled
(Initial value)
Rev. 3.00 Sep 27, 2006 page 209 of 872
REJ09B0325-0300