HD64F3048VTF8 Datasheet, PDF (272/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
Figure 8.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
CPU cycle
DMAC cycle
CPU
cycle DMAC cycle
T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
φ
DREQ
Address
bus
RD
HWR, LWR
Minimum 4 states
Next sampling point
Figure 8.16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode
Rev. 3.00 Sep 27, 2006 page 244 of 872
REJ09B0325-0300