HD64F3048VTF8 Datasheet, PDF (68/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 2 CPU
2.6 Instruction Set
2.6.1 Instruction Set Overview
The H8/300H CPU has 62 types of instructions, which are classified in table 2.1.
Table 2.1 Instruction Classification
Function
Data transfer
Instruction
MOV, PUSH^*1, POP^*1, MOVTPE^*2, MOVFPE^*2
Types
3
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,
18
DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS,
EXTU
Logic operations
AND, OR, XOR, NOT
4
Shift operations
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
14
BXOR, BIXOR, BLD, BILD, BST, BIST
Branch
Bcc^*3, JMP, BSR, JSR, RTS
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9
Block data transfer EEPMOV
1
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. Not available in the H8/3048B Group.
3. Bcc is a generic branching instruction.
Total 62 types
Rev. 3.00 Sep 27, 2006 page 40 of 872
REJ09B0325-0300