HD64F3048VTF8 Datasheet, PDF (469/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 12 Watchdog Timer
Section 12 Watchdog Timer
12.1 Overview
The H8/3048B Group has an on-chip watchdog timer (WDT). The WDT has two selectable
functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an
interval timer. As a watchdog timer, it generates a reset signal for the chip if a system crash allows
the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an
interval timer interrupt is requested at each TCNT overflow.
12.1.1 Features
WDT features are listed below.
• Selection of eight counter clock sources
φ/2, φ/32, φ/64, φ/128, φ/256, φ/512, φ/2048, or φ/4096
• Interval timer option
• Timer counter overflow generates a reset signal or interrupt.
The reset signal is generated in watchdog timer operation. An interval timer interrupt is
generated in interval timer operation.
• The entire chip can be reset internally by a reset signal output from the watchdog timer.
The reset signal generated by timer counter overflow during watchdog timer operation resets
the entire chip internally. In an H8/3048F-ONE (single power supply with flash memory), the
RESO pin acts as the FWE pin; no external reset signal can be output.
Rev. 3.00 Sep 27, 2006 page 441 of 872
REJ09B0325-0300