HD64F3048VTF8 Datasheet, PDF (887/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix C I/O Port Block Diagrams
Reset
R
Q
D
PB_n DDR
C
WPBD
Reset
TPC
R
TPC output
enable
PB _n
Q
D
PB _n DR
Next data
C
WPB
Output trigger
ITU
Output enable
Compare
match output
RPB
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
Note: n = 4 and 5
Figure C.11 (b) Port B Block Diagram (Pins PB₄ and PB₅)
Rev. 3.00 Sep 27, 2006 page 859 of 872
REJ09B0325-0300