HD64F3048VTF8 Datasheet, PDF (21/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

10.1.4 Register Configuration......................................................................................... 328
10.2 Register Descriptions ........................................................................................................ 331
10.2.1 Timer Start Register (TSTR)................................................................................ 331
10.2.2 Timer Synchro Register (TSNC) ......................................................................... 332
10.2.3 Timer Mode Register (TMDR) ............................................................................ 334
10.2.4 Timer Function Control Register (TFCR)............................................................ 337
10.2.5 Timer Output Master Enable Register (TOER) ................................................... 339
10.2.6 Timer Output Control Register (TOCR) .............................................................. 341
10.2.7 Timer Counters (TCNT) ...................................................................................... 342
10.2.8 General Registers A, B (GRA, GRB) .................................................................. 343
10.2.9 Buffer Registers A, B (BRA, BRB) ..................................................................... 344
10.2.10 Timer Control Registers (TCR) ........................................................................... 345
10.2.11 Timer I/O Control Register (TIOR) ..................................................................... 348
10.2.12 Timer Status Register (TSR)................................................................................ 350
10.2.13 Timer Interrupt Enable Register (TIER) .............................................................. 352
10.3 CPU Interface.................................................................................................................... 353
10.3.1 16-Bit Accessible Registers ................................................................................. 353
10.3.2 8-Bit Accessible Registers ................................................................................... 356
10.4 Operation .......................................................................................................................... 357
10.4.1 Overview.............................................................................................................. 357
10.4.2 Basic Functions.................................................................................................... 359
10.4.3 Synchronization ................................................................................................... 367
10.4.4 PWM Mode.......................................................................................................... 369
10.4.5 Reset-Synchronized PWM Mode......................................................................... 373
10.4.6 Complementary PWM Mode ............................................................................... 376
10.4.7 Phase Counting Mode .......................................................................................... 385
10.4.8 Buffering.............................................................................................................. 387
10.4.9 ITU Output Timing .............................................................................................. 392
10.5 Interrupts ........................................................................................................................... 395
10.5.1 Setting of Status Flags ......................................................................................... 395
10.5.2 Timing of Clearing of Status Flags ...................................................................... 398
10.5.3 Interrupt Sources and DMA Controller Activation.............................................. 398
10.6 Usage Notes ...................................................................................................................... 400
Section 11 Programmable Timing Pattern Controller............................................... 415
11.1 Overview........................................................................................................................... 415
11.1.1 Features................................................................................................................ 415
11.1.2 Block Diagram ..................................................................................................... 416
11.1.3 TPC Pins .............................................................................................................. 417
11.1.4 Registers............................................................................................................... 418
11.2 Register Descriptions ........................................................................................................ 419
Rev. 3.00 Sep 27, 2006 page xix of xxvi