HD64F3048VTF8 Datasheet, PDF (832/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix B Internal I/O Register
TCNT—Timer Counter
H'A9 (read),
H'A8 (write)
WDT
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
RSTCSR—Reset Control/Status Register
H'AB (read),
H'AA (write)
Bit
7
6
5
4
3
2
1
WRST RSTOE 




Initial value
0
0
1
1
1
1
1
Read/Write R/(W)* R/W





Reset output enable
0 External output of reset signal is disabled
1 External output of reset signal is enabled
Watchdog timer reset
0 [Clearing conditions]
• Reset signal input at RES pin
• When WRST = 1, write 0 after reading WRST flag
1 [Setting condition]
TCNT overflow generates a reset signal
Note: * Only 0 can be written in bit 7, to clear the flag.
H8/3048F-ONE
Not include this register
H8/3048B mask ROM version Include this register
H8/3048F
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
WDT
0

1

Rev. 3.00 Sep 27, 2006 page 804 of 872
REJ09B0325-0300