HD64F3048VTF8 Datasheet, PDF (797/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix B Internal I/O Register
FLMCR1—Flash Memory Control Register 1
H'40
Flash memory
Bit
Initial value*
Read/Write
7
FWE
1
R
6
SWE
0
R/W*
5
ESU
0
R/W*
4
PSU
0
R/W*
3
EV
0
R/W*
2
PV
0
R/W*
1
E
0
R/W*
0
P
0
R/W*
Program mode
0 Program mode cleared
(Initial value)
1 Transition to program mode
Erase mode
0 Erase mode cleared (Initial value)
1 Transition to erase mode
Program-verify mode
0 Program-verify mode cleared (Initial value)
1 Transition to program-verify mode
Erase-verify mode
0 Erase-verify mode cleared (Initial value)
1 Transition to erase-verify mode
Program setup bit
0 Program setup cleared
1 Program setup
(Initial value)
Erase setup bit
0 Erase setup cleared
1 Erase setup
(Initial value)
Software write enable bit
0 Write disabled (Initial value)
1 Write enabled
Flash write enable bit
0 When a low level is input to the FWE pin (hardware protection state)
1 When a high level is input to the FWE pin
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes 1, 2,
3, and 4 (on-chip flash memory disabled), this register cannot be modified and is always read
as H'FF.
H8/3048F-ONE
Include this register
H8/3048B mask ROM version
H8/3048F
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Not include this register
Rev. 3.00 Sep 27, 2006 page 769 of 872
REJ09B0325-0300