HD64F3048VTF8 Datasheet, PDF (394/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Input capture signal timing: Input capture on the rising edge, falling edge, or both edges can be
selected by settings in TIOR. Figure 10.25 shows the timing when the rising edge is selected. The
pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture,
and 2.5 system clocks for capture of both edges.
φ
Input-capture input
Internal input
capture signal
TCNT
N
GRA, GRB
N
Figure 10.25 Input Capture Signal Timing
Rev. 3.00 Sep 27, 2006 page 366 of 872
REJ09B0325-0300