HD64F3048VTF8 Datasheet, PDF (833/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

RSTCSR—Reset Control/Status Register
Bit
7
6
5
4
WRST



Initial value
0
0
1
1
Read/Write
R/(W)^*1  ^*2


Appendix B Internal I/O Register
H'AB (read),
H'AA (write)
WDT
3
2
1
0




1
1
1
1




Watchdog timer reset
0 [Clearing conditions]
• Reset signal input at RES pin
• When WRST = 1, write 0 after reading WRST flag
1 [Setting condition]
TCNT overflow generates a reset signal
Notes: 1. Only 0 can be written in bit 7, to clear the flag.
2. Bit 6 must not be set to 1; in a write, 0 must always be written in this bit.
H8/3048F-ONE
Include this register
H8/3048B mask ROM version Not include this register
H8/3048F
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Rev. 3.00 Sep 27, 2006 page 805 of 872
REJ09B0325-0300