HD64F3048VTF8 Datasheet, PDF (363/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
When MDF is set to 1 to select phase counting mode, TCNT2 operates as an up/down-counter and
pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling
edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction Down-Counting
Up-Counting
TCLKA pin
TCLKB pin
↑
High _↓
Low _↑
Low _↓
High
Low _↑
High _↓
High _↑
Low _↓
In phase counting mode channel 2 operates as above regardless of the external clock edges
selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in
TCR2. Phase counting mode takes precedence over these settings.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare
match/input capture settings and interrupt functions of TIOR2, TIER2, and TSR2 remain effective
in phase counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TSR2. The
FDIR designation is valid in all modes in channel 2.
Bit 5: FDIR
0
1
Description
OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
OVF is set to 1 in TSR2 when TCNT2 overflows
(Initial value)
Bit 4—PWM Mode 4 (PWM4): Selects whether channel 4 operates normally or in PWM mode.
Bit 4: PWM4
0
1
Description
Channel 4 operates normally
Channel 4 operates in PWM mode
(Initial value)
When bit PWM4 is set to 1 to select PWM mode, pin TIOCA₄ becomes a PWM output pin. The
output goes to 1 at compare match with GRA4, and to 0 at compare match with GRB4.
If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and
CMD0 in TFCR, the CMD1 and CMD0 setting takes precedence and the PWM4 setting is
ignored.
Rev. 3.00 Sep 27, 2006 page 335 of 872
REJ09B0325-0300