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HD64F3048VTF8 Datasheet, PDF (666/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip | |||
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Section 19 Clock Pulse Generator
19.5.3 Usage Notes
The DIVCR setting changes the Ï frequency, so note the following points.
⢠Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time tcyc in the AC electrical characteristics. Note that ÏMIN must be in the lower
limit of the clock frequency range. Avoid settings that give system clock frequencies less than
the lower limit.
Table 19.6 shows the comparison with the clock frequency range for each version.
Table 19.6 Comparison with the Clock Frequency Ranges in the H8/3048 Group and
H8/3048B Group
ROM type
F-ZTAT
ZTAT
Mask ROM
Product type
H8/3048
F-ONE
H8/3048F
H8/3048
H8/3048
Mask
ROM
Version
H8/3047 H8/3045 H8/3044 H8/3048B
Mask Mask Mask Mask
ROM ROM ROM ROM
Version Version Version Version
Guaranteed 4.5â5.5 V
clock
frequency 3.15â5.5 V
range
2â25
MHz
1â16
MHz
â
1â18
MHz
1â13
MHz
1â18 MHz
1â13 MHz
2â25
MHz
â
2.7â5.5 V
â
1â8
1â8
1â8 MHz
â
MHz
MHz
3.0â3.6 V 2â25
â
â
MHz
â
2â25
MHz
Crystal oscillation
range
2â25
MHz
2â16
MHz
2â18
MHz
2â18 MHz
2â25
MHz
⢠All on-chip module operations are based on Ï. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 20.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
Rev. 3.00 Sep 27, 2006 page 638 of 872
REJ09B0325-0300
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