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HD64F3048VTF8 Datasheet, PDF (745/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip
Mnemonic
Operation
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
— PC ← ERn
— PC ← aa:24
— PC ← @aa:8
— PC → @−SP
PC ← PC+d:8
— PC → @−SP
PC ← PC+d:16
— PC → @−SP
PC ← @ERn
— PC → @−SP
PC ← @aa:24
— PC → @−SP
PC ← @aa:8
— PC ← @SP+
Appendix A Instruction Set
Addressing Mode and
Instruction Length (bytes)
Condition Code
No. of
States*1
I HNZVC
2
 4
4
 6
2
      8 10
2
 6 8
4
      8 10
2
 6 8
4
      8 10
2
      8 12
2       8 10
Rev. 3.00 Sep 27, 2006 page 717 of 872
REJ09B0325-0300