HD64F3048VTF8 Datasheet, PDF (271/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
Figure 8.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three
words from a 16-bit two-state access area to another 16-bit two-state access area.
CPU cycle
DMAC cycle
CPU cycle
T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂
φ
Address
bus
RD
Source Destination
address address
HWR,
LWR
Figure 8.15 Bus Timing of Burst Mode DMA Transfer
When the DMAC is activated from a DREQ pin there is a minimum interval of four states from
when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled
during the time between the transfer request and the start of the transfer. In short address mode and
normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the pin
is next sampled at the end of one block transfer.
Rev. 3.00 Sep 27, 2006 page 243 of 872
REJ09B0325-0300