HD64F3048VTF8 Datasheet, PDF (673/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

20.3 Sleep Mode
Section 20 Power-Down State
20.3.1 Transition to Sleep Mode
When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a
transition from the program execution state to sleep mode. Immediately after executing the SLEEP
instruction the CPU halts, but the contents of its internal registers are retained. The DMA
controller (DMAC), refresh controller, and on-chip supporting modules do not halt in sleep mode.
Modules which have been placed in standby by the module standby function, however, remain
halted.
20.3.2 Exit from Sleep Mode
Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt other than NMI if the interrupt is masked by the I and UI bits in CCR and IPR.
Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state.
Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
20.4 Software Standby Mode
20.4.1 Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules
are reset. As long as the specified voltage is supplied, however, CPU register contents and on-chip
RAM data are retained. The settings of the I/O ports and refresh controller* are also held.
Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their
previous states.
Rev. 3.00 Sep 27, 2006 page 645 of 872
REJ09B0325-0300