HD64F3048VTF8 Datasheet, PDF (460/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 11 Programmable Timing Pattern Controller
11.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 11.3 shows the timing of these operations
for the case of normal output in groups 2 and 3, triggered by compare match A.
φ
TCNT
GRA
Compare
match A signal
NDRB
N
N+1
N
n
PBDR
m
n
TP₈ to TP₁₅
m
n
Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)
Rev. 3.00 Sep 27, 2006 page 432 of 872
REJ09B0325-0300