HD64F3048VTF8 Datasheet, PDF (149/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
In this situation, conduct one of the following countermeasures.
Countermeasure 1: When clears IRQaF flag, do not use the bit manipulation instruction, read the
ISR in bytes. Then write a value in bytes which sets IRQaF flag to 0 and other bits to 1.
For example, if a = 0
MOV.B @ISR,R0L
MOV.B #HFE,R0L
MOV.B R0L,@ISR
Countermeasure 2: During IRQb interrupt exception processing, carry out IRQbF flag clear
dummy processing.
For example, if b = 1
IRQB
MOV.B #HFD,R0L
MOV.B R0L,@ISR
···
5.5.5 Notes on Non-Maskable Interrupts (NMI)
NMI is an exception processing that can be executed by the interrupt controller and CPU when the
chip internal circuits are operating normally under a specified electrical characteristics. If an NMI
is executed when the circuits are not operating normally due to some factors such as software or
abnormal interrupt of input to the pins (runaway execution), the operation will not be guaranteed.
Incorrect NMI Operation Factors: Software
1. When an interrupt exception processing is executed in an H8/300H CPU, it is assumed that the
stack pointer (SP(ER7)) has already been set by software, and that the stack pointer (SP(ER7))
points to the stack area set in a system such as RAM. If the program is in a runaway execution,
the stack pointer may be overflowed and updated illegally. Therefore, normal operation will
not be guaranteed.
2. Requests for NMIs can be accepted on the rising or falling edge of a pin. Acceptance of the
rising or falling edge depends on the setting of the bit NMIEG in the system control register
(SYSCR). It is necessary for the customer to set the bit according to the designated system.
When the program is in a runaway execution, this bit may be rewritten illegally. Therefore, the
system may not operate as expected.
Rev. 3.00 Sep 27, 2006 page 121 of 872
REJ09B0325-0300