HD64F3048VTF8 Datasheet, PDF (200/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
When a refresh request occurs in the refresh request pending state, the refresh controller acquires
the bus right, then executes a refresh cycle. If another refresh request occurs during execution of
the refresh cycle, it is ignored.
Exit from reset or standby mode
Refresh
request*
Refresh
request*
Refresh request
Refresh request pending state
Refresh request
Requesting bus right
End of refresh
cycle*
Bus granted
Executing refresh cycle
Note: * A refresh request is ignored if it occurs while the refresh controller is requesting the
bus right or executing a refresh cycle.
Figure 7.3 State Transitions for Refresh Cycle Execution
Address Multiplexing
Address multiplexing depends on the setting of the M9/M8 bit in RFSHCR, as described in table
7.5. Figure 7.4 shows the address output timing. Address output is multiplexed only in area 3.
Rev. 3.00 Sep 27, 2006 page 172 of 872
REJ09B0325-0300