HD64F3048VTF8 Datasheet, PDF(190/903 Page) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

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HD64F3048VTF8 Datasheet, PDF (190/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

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Section 7 Refresh Controller

7.1.3 Input/Output Pins

Table 7.1 summarizes the refresh controllerâs input/output pins.

Table 7.1 Refresh Controller Pins

Pin Name

RFSH Refresh

Signal

Abbr.

RFSH

I/O

Output

HWR

LWR

RD

CS3

Upper write/upper column

address strobe

Lower write/lower column

address strobe

Column address strobe/

write enable

Row address strobe

UW/UCAS

LW/LCAS

CAS/WE

RAS

Output

Output

Output

Output

Function

Goes low during refresh cycles;

used to refresh DRAM and PSRAM

Connects to the UW pin of 2WE

DRAM or UCAS pin of 2CAS DRAM

Connects to the LW pin of 2WE

DRAM or LCAS pin of 2CAS DRAM

Connects to the CAS pin of 2WE

DRAM or WE pin of 2CAS DRAM

Connects to the RAS pin of DRAM

7.1.4 Register Configuration

Table 7.2 summarizes the refresh controllerâs registers.

Table 7.2 Refresh Controller Registers

Address* Name

H'FFAC

Refresh control register

H'FFAD

Refresh timer control/status register

H'FFAE

Refresh timer counter

H'FFAF

Refresh time constant register

Note: * Lower 16 bits of the address.

Abbreviation R/W

RFSHCR

R/W

RTMCSR

R/W

RTCNT

R/W

RTCOR

R/W

Initial Value

H'02

H'07

H'00

H'FF

Rev. 3.00 Sep 27, 2006 page 162 of 872

REJ09B0325-0300

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