HD64F3048VTF8 Datasheet, PDF (293/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 9 I/O Ports
P1DDR is initialized to H'FF in modes 1 to 4 and H'00 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting. If a P1DDR bit is set to 1,
the corresponding pin maintains its output state in software standby mode.
Port 1 Data Register (P1DR)
P1DR is an 8-bit readable/writable register that stores output data for pins P1₇ to P1₀. While port 1
acts as an output port, the value of this register is output. When a bit in P1DDR is set to 1, if port 1
is read the value of the corresponding P1DR bit is returned. When a bit in P1DDR is cleared to 0,
if port 1 is read the corresponding pin level is read.
Bit
Initial value
Read/Write
7
P1₇
0
R/W
6
5
4
3
2
1
0
P1₆
P1₅
P1₄
P1₃
P1₂
P1₁
P1₀
0
0
0
0
0
0
0
R/W
R/W
R/W R/W
R/W
R/W R/W
Port 1 data 7 to 0
These bits store data for port 1 pins
P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 3.00 Sep 27, 2006 page 265 of 872
REJ09B0325-0300