HD64F3048VTF8 Datasheet, PDF (26/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

18.14 Notes when Converting the F-ZTAT (Single Power Supply) Application Software
to the Mask-ROM Versions .............................................................................................. 627
Section 19 Clock Pulse Generator .................................................................................. 629
19.1 Overview........................................................................................................................... 629
19.1.1 Block Diagram ..................................................................................................... 630
19.2 Oscillator Circuit............................................................................................................... 630
19.2.1 Connecting a Crystal Resonator........................................................................... 630
19.2.2 External Clock Input ............................................................................................ 633
19.3 Duty Adjustment Circuit................................................................................................... 636
19.4 Prescalers .......................................................................................................................... 636
19.5 Frequency Divider ............................................................................................................ 636
19.5.1 Register Configuration......................................................................................... 637
19.5.2 Division Control Register (DIVCR) .................................................................... 637
19.5.3 Usage Notes ......................................................................................................... 638
Section 20 Power-Down State ......................................................................................... 639
20.1 Overview........................................................................................................................... 639
20.2 Register Configuration...................................................................................................... 641
20.2.1 System Control Register (SYSCR) ...................................................................... 641
20.2.2 Module Standby Control Register (MSTCR)....................................................... 643
20.3 Sleep Mode ....................................................................................................................... 645
20.3.1 Transition to Sleep Mode..................................................................................... 645
20.3.2 Exit from Sleep Mode.......................................................................................... 645
20.4 Software Standby Mode.................................................................................................... 645
20.4.1 Transition to Software Standby Mode ................................................................. 645
20.4.2 Exit from Software Standby Mode ...................................................................... 646
20.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 646
20.4.4 Sample Application of Software Standby Mode.................................................. 648
20.4.5 Note...................................................................................................................... 648
20.5 Hardware Standby Mode .................................................................................................. 649
20.5.1 Transition to Hardware Standby Mode ................................................................ 649
20.5.2 Exit from Hardware Standby Mode ..................................................................... 649
20.5.3 Timing for Hardware Standby Mode ................................................................... 649
20.6 Module Standby Function ................................................................................................. 650
20.6.1 Module Standby Timing ...................................................................................... 650
20.6.2 Read/Write in Module Standby............................................................................ 650
20.6.3 Usage Notes ......................................................................................................... 651
20.7 System Clock Output Disabling Function......................................................................... 652
Rev. 3.00 Sep 27, 2006 page xxiv of xxvi