HD64F3048VTF8 Datasheet, PDF (434/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, the counter is
cleared according to the input capture signal. The counter is not incremented by the increment
signal. The value before the counter is cleared is transferred to the general register. See figure
10.67.
φ
Input capture signal
Counter clear signal
TCNT input clock
TCNT
N
H'0000
GR
N
Figure 10.67 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev. 3.00 Sep 27, 2006 page 406 of 872
REJ09B0325-0300