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| HD64F3048VTF8 Datasheet, PDF (69/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip | |||
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2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU.
Table 2.2 Instructions and Addressing Modes
Addressing Modes
Function
Instruction
Section 2 CPU
Data
transfer
MOV
POP, PUSH
MOVFPE*,
MOVTPE*
BWL BWL BWL BWL BWL BWL B BWL BWL â â â â
â â â â â â â â â â â â WL
âââââââ B âââââ
Arithmetic ADD, CMP
operations SUB
BWL BWL â â â â â â â â â â â
WL BWL â â â â â â â â â â â
ADDX, SUBX
B
B âââââââââââ
ADDS, SUBS
â L âââââââââââ
INC, DEC
â BWL â â â â â â â â â â â
DAA, DAS
â B âââââââââââ
MULXU, MULXS, â BW â â â â â â â â â â â
DIVXU, DIVXS
NEG
â BWL â â â â â â â â â â â
EXTU, EXTS
â WL â â â â â â â â â â â
Logic
AND, OR, XOR BWL BWL â â â â â â â â â â â
operations NOT
â BWL â â â â â â â â â â â
Shift instructions
â BWL â â â â â â â â â â â
Bit manipulation
â
B
B
âââ B
ââââââ
Branch Bcc, BSR
âââââââââ
ââ
JMP, JSR
ââ
âââââ
ââ
â
RTS
ââââââââââââ
System
control
TRAPA
RTE
ââââââââââââ
ââââââââââââ
SLEEP
ââââââââââââ
LDC
B
B
W W W W âW W ââââ
STC
â B WWWWâWWââââ
ANDC, ORC,
XORC
B ââââââââââââ
NOP
ââââââââââââ
Block data transfer
â â â â â â â â â â â â BW
Legend:
B: Byte
W: Word
L: Longword
Note: * Not availabe in the H8/3048B Group.
Rev. 3.00 Sep 27, 2006 page 41 of 872
REJ09B0325-0300
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