HD64F3048VTF8 Datasheet, PDF (539/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 13 Serial Communication Interface
16 clocks
Internal
base clock
8 clocks
0
7
15 0
7
15 0
Receive data
(RxD)
Start bit
D₀
D₁
Synchronization
sampling timing
Data sampling
timing
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as in equation (1).
M = (0.5 − ¹ ) − (L − 0.5) F − ^{D − 0.5} (1 + F) × 100% _{................... (1)}
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = {0.5 – 1/(2 × 16)} × 100%
= 46.875% ............................................................................................. (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Usage of DMAC
To have the DMAC read RDR, be sure to select the SCI receive-data-full interrupt (RXI) as the
activation source with bits DTS2 to DTS0 in DTCR.
Rev. 3.00 Sep 27, 2006 page 511 of 872
REJ09B0325-0300