HD64F3048VTF8 Datasheet, PDF (349/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Table 10.1 summarizes the ITU functions.
Table 10.1 ITU Functions
Item
Clock sources
General registers
(output compare/input
capture registers)
Buffer registers
Input/output pins
Output pins
Counter clearing function
Compare match 0
output
1
Toggle
Input capture function
Synchronization
PWM mode
Reset-synchronized
PWM mode
Complementary PWM
mode
Phase counting mode
Buffering
DMAC activation
Interrupt sources
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently
GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4
—
TIOCA₀,
TIOCB₀
—
GRA0/GRB0
compare
match or
input capture
O
O
O
O
O
O
—
—
TIOCA₁,
TIOCB₁
—
GRA1/GRB1
compare
match or
input capture
O
O
O
O
O
O
—
—
TIOCA₂,
TIOCB₂
—
GRA2/GRB2
compare
match or
input capture
O
O
—
O
O
O
—
BRA3, BRB3
TIOCA₃,
TIOCB₃
—
GRA3/GRB3
compare
match or
input capture
O
O
O
O
O
O
O
BRA4, BRB4
TIOCA₄,
TIOCB₄
TOCXA₄,
TOCXB₄
GRA4/GRB4
compare
match or
input capture
O
O
O
O
O
O
O
—
—
—
O
O
—
—
O
—
—
—
—
—
O
O
GRA0 compare GRA1 compare GRA2 compare GRA3 compare —
match or input match or input match or input match or input
capture
capture
capture
capture
Three sources Three sources Three sources Three sources Three sources
• tch/input
capture A0
• Compare
match/input
capture B0
• Overflow
• Compare
match/input
capture A1
• Compare
match/input
capture B1
• Overflow
• Compare
match/input
capture A2
• Compare
match/input
capture B2
• Overflow
• Compare
match/input
capture A3
• Compare
match/input
capture B3
• Overflow
• Compare
match/input
capture A4
• Compare
match/input
capture B4
• Overflow
Legend: O: Available
—: Not available
Rev. 3.00 Sep 27, 2006 page 321 of 872
REJ09B0325-0300