HD64F3048VTF8 Datasheet, PDF (552/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 14 Smart Card Interface
V_CC
TxD₀
RxD₀
SCK₀
Px (port)
H8/3048B Group
Data line
Clock line
Reset line
I/O
CLK
RST
Smart card
Card-processing device
Figure 14.2 Smart Card Interface Connection Diagram
Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a
smart card.
14.3.3 Data Format
Figure 14.3 shows the data format of the smart card interface. In receive mode, parity is checked
once per frame. If a parity error is detected, an error signal is returned to the transmitting device to
request retransmission. In transmit mode, the error signal is sampled and the same data is
retransmitted if the error signal is low.
Rev. 3.00 Sep 27, 2006 page 524 of 872
REJ09B0325-0300