HD64F3048VTF8 Datasheet, PDF (428/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
10.6 Usage Notes
This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear
If a counter clear signal occurs in the T₃ state of a TCNT write cycle, clearing of the counter takes
priority and the write is not performed. See figure 10.61.
TCNT write cycle
T₁
T₂
T₃
φ
Address bus
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'0000
Figure 10.61 Contention between TCNT Write and Clear
Rev. 3.00 Sep 27, 2006 page 400 of 872
REJ09B0325-0300