HD64F3048VTF8 Datasheet, PDF (186/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 6 Bus Controller
6.4.3 BREQ Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes low, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
6.4.4 Transition To Software Standby Mode
If contention occurs between a transition to software standby mode and a bus request from an
external bus master, the bus may be released for one state just before the transition to software
standby mode (see figure 6.23). When using software standby mode, clear the BRLE bit to 0 in
BRCR before executing the SLEEP instruction.
φ
BREQ
BACK
Address bus
Strobe
Bus-released state Software standby mode
Figure 6.23 Contention between Bus-Released State and Software Standby Mode
Rev. 3.00 Sep 27, 2006 page 158 of 872
REJ09B0325-0300