HD64F3048VTF8 Datasheet, PDF (348/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
• Three additional modes selectable in channels 3 and 4
 Reset-synchronized PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
complementary waveforms.
 Complementary PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
non-overlapping complementary waveforms.
 Buffering
Input capture registers can be double-buffered. Output compare registers can be updated
automatically.
• High-speed access via internal 16-bit bus
The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed
via a 16-bit bus.
• Fifteen interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
• Activation of DMA controller (DMAC)
Four of the compare match/input capture interrupts from channels 0 to 3 can start the DMAC.
• Output triggering of programmable timing pattern controller (TPC)
Compare match/input capture signals from channels 0 to 3 can be used as TPC output triggers.
Rev. 3.00 Sep 27, 2006 page 320 of 872
REJ09B0325-0300