HD64F3048VTF8 Datasheet, PDF (159/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 6 Bus Controller
Bit 5—Address 21 Enable (A21E): Enables PA₆ to be used as the A₂₁ address output pin. Writing
0 in this bit enables A₂₁ address output from PA₆. In modes other than 3, 4, and 6 this bit cannot be
modified and PA₆ has its ordinary input/output functions.
Bit 5: A21E
0
1
Description
PA₆ is the A₂₁ address output pin
PA is the PA /TP /TIOCA input/output pin
6
6
6
2
(Initial value)
Bits 4 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0: BRLE
0
1
Description
The bus cannot be released to an external device; BREQ and BACK can be
used as input/output pins
(Initial value)
The bus can be released to an external device
Rev. 3.00 Sep 27, 2006 page 131 of 872
REJ09B0325-0300