HD64F3048VTF8 Datasheet, PDF (369/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
10.2.6 Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.
Bit
7

Initial value
1
Read/Write

6
5
4
3


XTGD

1
1
1
1


R/W

2
1
0

OLS4 OLS3
1
1
1

R/W R/W
Reserved bits
Output level select 3, 4
These bits select output
levels in complementary
PWM mode and reset-
synchronized PWM mode
Reserved bits
External trigger disable
Selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized
PWM mode
The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode
and reset-synchronized PWM mode. These settings do not affect other modes.
TOCR is initialized to H'FF by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output
in complementary PWM mode and reset-synchronized PWM mode.
Bit 4: XTGD
0
1
Description
Input capture A in channel 1 is used as an external trigger signal in
complementary PWM mode and reset-synchronized PWM mode.
When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling
ITU output.
External triggering is disabled
(Initial value)
Bits 3 and 2—Reserved: Read-only bits, always read as 1.
Rev. 3.00 Sep 27, 2006 page 341 of 872
REJ09B0325-0300