HD64F3048VTF8 Datasheet, PDF (535/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 13 Serial Communication Interface
Initialize
1
1. SCI initialization: the transmit data
output function of the TxD pin and
Start transmitting and receiving
receive data input function of the
RxD pin are selected, enabling
simultaneous transmitting and
receiving.
Read TDRE flag in SSR
2
2. SCI status check and transmit
data write: read SSR, check that
the TDRE flag is 1, then write
No
TDRE = 1?
transmit data in TDR and clear
the TDRE flag to 0.
Notification that the TDRE flag has
Yes
changed from 0 to 1 can also be
given by the TXI interrupt.
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
3. Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the neces-
sary error handling, clear the ORER
flag to 0.
Neither transmitting nor receiving
Read ORER flag in SSR
can resume while the ORER flag
remains set to 1.
4. SCI status check and receive
ORER = 1?
Yes
3
data read: read SSR, check that
the RDRF flag is 1, then read
receive data from RDR and clear
the RDRF flag to 0. Notification
No
Error handling
that the RDRF flag has changed
from 0 to 1 can also be given
Read RDRF flag in SSR
by the RXI interrupt.
4
5. To continue transmitting and
receiving serial data: check the
No
RDRF = 1?
RDRF flag, read RDR, and clear
the RDRF flag to 0 before the
MSB (bit 7) of the current frame
is received. Also check that
Yes
the TDRE flag is set to 1, indicat-
ing that data can be written, write
Read receive data from RDR
and clear RDRF flag to 0 in SSR
data in TDR, then clear the TDRE
flag to 0 before the MSB (bit 7) of
the current frame is transmitted.
When the DMAC is activated by
a transmit-data-empty interrupt
No
End of transmitting and
receiving?
5
request (TXI) to write data in TDR,
the TDRE flag is checked and
cleared automatically. When the
Yes
DMAC is activated by a receive-
data-full interrupt request (RXI) to
Clear TE and RE bits to 0 in SCR
read RDR, the RDRF flag is
cleared automatically.
End
Note: When switching from transmitting or receiving to simultaneous
transmitting and receiving, clear both the TE bit and the RE bit
to 0, then set both bits to 1.
Figure 13.20 Sample Flowchart for Serial Transmitting
Rev. 3.00 Sep 27, 2006 page 507 of 872
REJ09B0325-0300