HD64F3048VTF8 Datasheet, PDF (211/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
Set area 3 for 16-bit access
Set P8₁ DDR to 1 for CS₃ output
Set RTCOR
Set bits CKS2 to CKS0 in RTMCSR
Write H'3B in RFSHCR
Wait for DRAM to be initialized
DRAM can be accessed
Figure 7.12 Setup Procedure for 2CAS 4-Mbit DRAM with 9-Bit Row Address and 9-Bit
Column Address (16-Mbyte Mode)
Example 4: Connection to Multiple 4-Mbit DRAM Chips (16-Mbyte Mode)
Figure 7.13 shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the
corresponding address map. Up to four DRAM chips can be connected to area 3 by decoding
upper address bits A₁₉ and A₂₀.
Figure 7.14 shows a setup procedure to be followed by a program for this example. The DRAM in
this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed
simultaneously, so the RFSH pin must be used.
Rev. 3.00 Sep 27, 2006 page 183 of 872
REJ09B0325-0300