HD64F3048VTF8 Datasheet, PDF (148/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
• Occurrence conditions
1. When IRQaF = 1, for the IRQaF flag to clear, ISR register read is executed. Thereafter
interrupt processing is carried out and IRQbF flag clears.
2. IRQaF flag clear and IRQbF flag generation compete (IRQaF flag setting).
(The ISR read needed for IRQaF flag clear was at IRQbF = 0 but in the time taken for ISR
write, IRQbF = 1 was reached.)
In all of the setting conditions 1 to 3 and occurrence conditions 1 and 2 are generated, IRQbF
clears in error during ISR write for occurrence condition 2 and interrupt processing is not carried
out. However, if IRQbF flag reaches 0 between occurrence conditions 1 and 2, IRQbF flag does
not clear in error.
IRQaF
IRQbF
Read Write
10
Read Write
1
0
Read Write IRQb
11
Execution
Occurrence condition 1
Read Write
0
0
Clear in error
Occurrence condition 2
Figure 5.9 IRQnF Flag When Interrupt Processing Is Not Conducted
Rev. 3.00 Sep 27, 2006 page 120 of 872
REJ09B0325-0300