HD64F3048VTF8 Datasheet, PDF (487/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

13.2 Register Descriptions
13.2.1 Receive Shift Register (RSR)
RSR is the register that receives serial data.
Bit
7
6
5
Section 13 Serial Communication Interface
4
3
2
1
0
Read/Write








The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When 1 byte has been received, it is automatically
transferred to RDR. The CPU cannot read or write RSR directly.
13.2.2 Receive Data Register (RDR)
RDR is the register that stores received serial data.
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
When the SCI finishes receiving 1 byte of serial data, it transfers the received data from RSR into
RDR for storage. RSR is then ready to receive the next data. This double buffering allows data to
be received continuously.
RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to
H'00 by a reset and in standby mode.
Rev. 3.00 Sep 27, 2006 page 459 of 872
REJ09B0325-0300