HD64F3048VTF8 Datasheet, PDF (152/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 6 Bus Controller
6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
CS₇ to CS₀
Internal
address bus
Area
decoder
Chip select
control signals
ABWCR
ASTCR
WCER
CSCR
Bus control
circuit
Internal signals
Bus mode control signal
Bus size control signal
Access state control signal
Wait request signal
WAIT
Wait-state
controller
WCR
Internal signals
CPU bus request signal
DMAC bus request signal
Refresh controller bus request signal
CPU bus acknowledge signal
DMAC bus acknowledge signal
Refresh controller bus acknowledge signal
BRCR
Bus arbiter
Legend:
ABWCR: Bus width control register
ASTCR: Access state control register
WCER: Wait state controller enable register
WCR: Wait control register
BRCR: Bus release control register
CSCR: Chip select control register
BACK
BREQ
Figure 6.1 Block Diagram of Bus Controller
Rev. 3.00 Sep 27, 2006 page 124 of 872
REJ09B0325-0300