HD64F3048VTF8 Datasheet, PDF (423/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
10.5 Interrupts
The ITU has two types of interrupts: input capture/compare match interrupts, and overflow
interrupts.
10.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match
IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general
register (GR). The compare match signal is generated in the last state in which the values match
(when TCNT is updated from the matching count to the next count). Therefore, when TCNT
matches a general register, the compare match signal is not generated until the next timer clock
input. Figure 10.57 shows the timing of the setting of IMFA and IMFB.
φ
TCNT input
clock
TCNT
N
N+1
GR
N
Compare
match signal
IMF
IMI
Figure 10.57 Timing of Setting of IMFA and IMFB by Compare Match
Rev. 3.00 Sep 27, 2006 page 395 of 872
REJ09B0325-0300