HD64F3048VTF8 Datasheet, PDF(417/903 Page) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

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HD64F3048VTF8 Datasheet, PDF (417/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

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TCNT value

GRB

H'0250

H'0200

H'0100

H'0000

BRA

H'0200

GRA

H'0250

TIOCB

TIOCA

Section 10 16-Bit Integrated Timer Unit (ITU)

Counter cleared by compare match B

H'0100

H'0200

H'0100

H'0200

H'0200

Time

Toggle

output

Toggle

output

Compare match A

Figure 10.49 Register Buffering (Example 1: Buffering of Output Compare Register)

Ï

TCNT

Compare

match signal

Buffer transfer

signal

BR

n

n+1

N

GR

n

N

Figure 10.50 Compare Match and Buffer Transfer Timing (Example)

Figure 10.51 shows an example in which GRA is set to function as an input capture register

buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the

input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because

Rev. 3.00 Sep 27, 2006 page 389 of 872

REJ09B0325-0300

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