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HD64F3048VTF8 Datasheet, PDF (886/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip
Appendix C I/O Port Block Diagrams
C.11 Port B Block Diagrams
Reset
R
Q
D
PBn DDR
C
WPBD
Reset
R
PB n
Q
D
PB n DR
C
WPB
TPC
TPC output
enable
Next data
Output trigger
ITU
Output enable
Compare
match output
RPB
Legend:
WPBD: Write to PBDDR
WPB: Write to port B
RPB: Read port B
Note: n = 0 to 3
Figure C.11 (a) Port B Block Diagram (Pins PB0 to PB3)
Input
capture
Rev. 3.00 Sep 27, 2006 page 858 of 872
REJ09B0325-0300