HD64F3048VTF8 Datasheet, PDF (247/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the
data transfer activation source. The selectable activation sources differ between normal mode and
block transfer mode.
• Normal mode
Bit 2:
DTS2B
0
1
Bit 1:
DTS1B
0
1
0
1
Bit 0:
DTS0B
0
1
0
1
0
1
0
1
Description
Auto-request (burst mode)
Cannot be used
Auto-request (cycle-steal mode)
Cannot be used
Cannot be used
Cannot be used
Falling edge of DREQ
Low level input at DREQ
(Initial value)
• Block transfer mode
Bit 2:
DTS2B
0
Bit 1:
DTS1B
0
1
1
0
1
Bit 0:
DTS0B
0
1
0
1
0
1
0
1
Description
Compare match/input capture A interrupt from ITU
channel 0
(Initial value)
Compare match/input capture A interrupt from ITU
channel 1
Compare match/input capture A interrupt from ITU
channel 2
Compare match/input capture A interrupt from ITU
channel 3
Cannot be used
Cannot be used
Falling edge of DREQ
Cannot be used
The same internal interrupt can be selected to activate two or more channels. The channels are
activated in a priority order, highest priority first. For the priority order, see section 8.4.9, DMAC
Multiple-Channel Operation.
Rev. 3.00 Sep 27, 2006 page 219 of 872
REJ09B0325-0300