HD64F3048VTF8 Datasheet, PDF (634/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
Write pulse application subroutine
Sub-Routine Write Pulse
WDT enable
Set PSU in FLMCR1
Wait (tspsu) µs
*7
Set P bit in FLMCR1
Start of programming
Wait (tsp) µs
Clear P bit in FLMCR1
*5 *7
Programming halted
Wait (tcp) µs
*7
Start of programming
START
Set SWE bit in FLMCR1
Wait (tsswe) µs
Store 128-byte program data in program
data area and reprogram data area
n= 1
m= 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Sub-Routine-Call
Write pulse
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*7
*4
*1
See Note 6 for pulse width
Clear PSU bit in FLMCR1
Wait (tcpsu) µs
*7
Disable WDT
End Sub
Note: 6. Write Pulse Width
Number of Writes n Write Time (tsp) µsec
1
30
2
30
3
30
4
30
5
30
6
30
7
200
8
200
9
200
10
200
11
200
12
200
13
200
Increment
address
998
200
999
200
1000
200
Note: Use a 10 µs write pulse for additional programming.
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Set PV bit in FLMCR1
Wait (tspv) µs
*7
H'FF dummy write to verify address
Wait (tspvr) µs
*7
Read verify data
*2
Write data = verify data?
NG
OK
6≥n?
NG
OK
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
*4
m=1
n←n+1
Reprogram data computation
*3
Transfer reprogram data to reprogram data area *4
128-byte data
NG
verification completed?
OK
Clear PV bit in FLMCR1
Wait (tcpv) µs
*7
6 ≥ n?
NG
OK
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
*1
Sub-Routine-Call
Write Pulse (Additional programming)
m=0?
NG
OK
Clear SWE bit in FLMCR1
Wait (tcswe) µs
End of programming
Reprogram
*7
n ≥ N?
NG
OK
Clear SWE bit in FLMCR1
Wait (tcswe) µs
*7
Programming failure
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data).
Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be
subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of
additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The wait times and value of N are shown in section 21.1.6, Flash Memory Characteristics.
Reprogram Data Computation Table
Original Data Verify Data Reprogram Data
(D)
(V)
(X)
Comments
0
0
1
Programming completed
0
1
0
Programming incomplete;
reprogram
1
0
1
1
1
1
Still in erased state;
no action
Additional-Programming Data Computation Table
Reprogram Data Verify Data
Additional-
(X')
(V)
Programming Data (Y)
Comments
0
0
0
Additional programming
to be executed
0
1
1
Additional programming
not to be executed
1
0
1
Additional programming
not to be executed
1
1
1
Additional programming
not to be executed
Figure 18.13 Program/Program-Verify Flowchart (128-Byte Programming)
Rev. 3.00 Sep 27, 2006 page 606 of 872
REJ09B0325-0300