HD64F3048VTF8 Datasheet, PDF (351/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Block Diagram of Channels 0 and 1
ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 10.2.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Clock selector
Comparator
Control logic
TIOCA₀
TIOCB₀
IMIA0
IMIB0
OVI0
Module data bus
Legend:
TCNT:
Timer counter (16 bits)
GRA, GRB: General registers A and B (input capture/output compare registers) (16 bits × 2)
TCR:
Timer control register (8 bits)
TIOR:
TIER:
TSR:
Timer I/O control register (8 bits)
Timer interrupt enable register (8 bits)
Timer status register (8 bits)
Figure 10.2 Block Diagram of Channels 0 and 1 (for Channel 0)
Rev. 3.00 Sep 27, 2006 page 323 of 872
REJ09B0325-0300