HD64F3048VTF8 Datasheet, PDF (861/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

SYSCR—System Control Register
Appendix B Internal I/O Register
H'F2
System control
Bit
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0 UE NMIEG  RAME
Initial value
0
0
0
0
1
0
1
1
Read/Write
R/W
R/W R/W R/W R/W R/W

R/W
RAM enable
0 On-chip RAM is disabled
1 On-chip RAM is enabled
NMI edge select
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
User bit enable
0 CCR bit 6 (UI) is used as an interrupt mask bit
1 CCR bit 6 (UI) is used as a user bit
Standby timer select 2 to 0
Bit 6 Bit 5 Bit 4
Standby Timer
STS2 STS1 STS0
H8/3048F-ONE
H8/3048B mask ROM version
*
0
0
0 Waiting time = 8,192 states Waiting time = 8,192 states
1 Waiting time = 16,384 states Waiting time = 16,384 states
1
0 Waiting time = 32,768 states Waiting time = 32,768 states
1 Waiting time = 65,536 states Waiting time = 65,536 states
1
0
0 Waiting time = 131,072 states Waiting time = 131,072 states
1 Waiting time = 262,144 states Waiting time = 1,024 states
1
0 Waiting time = 1,024 states Illegal setting
1 Illegal setting
Illegal setting
Note: * H8/3048F
H8/3048ZTAT
H8/3048 mask ROM version
H8/3047 mask ROM version
H8/3045 mask ROM version
H8/3044 mask ROM version
Software standby
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
Rev. 3.00 Sep 27, 2006 page 833 of 872
REJ09B0325-0300