HD64F3048VTF8 Datasheet, PDF (198/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
DRAM Interface
To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR, RTMCSR, and
RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1. Set bit P8₁DDR to
1 in the port 8 data direction register (P8DDR) to enable CS₃ output. In ABWCR, make area 3 a
16-bit-access area.
Pseudo-Static RAM Interface
To set up area 3 for connection to pseudo-static RAM, initialize RTCOR, RTMCSR, and
RFSHCR in that order, setting bit PSRAME to 1 and clearing bit DRAME to 0. Set bit P8₁DDR to
1 in P8DDR to enable CS₃ output.
Interval Timer
When PSRAME = 0 and DRAME = 0, the refresh controller operates as an interval timer. After
setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1. CMI interrupts will
be requested at compare match intervals determined by RTCOR and bits CKS2 to CKS0 in
RTMCSR.
When setting RTCOR, RTMCSR, and RFSHCR, make sure that PSRAME = 0 and DRAME = 0.
Writing is disabled when either of these bits is set to 1.
Rev. 3.00 Sep 27, 2006 page 170 of 872
REJ09B0325-0300