HD64F3048VTF8 Datasheet, PDF (757/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access Access Operation
I
J
K
L
M
N
INC
INC.B Rd
1
INC.W #1/2, Rd
1
INC.L #1/2, ERd
1
JMP
JMP @ERn
2
JMP @aa:24
2
2
JMP @@aa:8 Normal^*1 2
1
2
Advanced 2
2
2
JSR
JSR @ERn Normal^*1 2
1
Advanced 2
2
JSR @aa:24 Normal^*1 2
1
2
Advanced 2
2
2
JSR @@aa:8 Normal^*1 2
1
1
Advanced 2
2
2
LDC
LDC #xx:8, CCR
1
LDC Rs, CCR
1
LDC @ERs, CCR
2
1
LDC @(d:16, ERs), CCR 3
1
LDC @(d:24, ERs), CCR 5
1
LDC @ERs+, CCR
2
1
2
LDC @aa:16, CCR
3
1
LDC @aa:24, CCR
4
1
MOV
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @ERs, Rd
1
1
MOV.B @(d:16, ERs), Rd 2
1
MOV.B @(d:24, ERs), Rd 4
1
MOV.B @ERs+, Rd
1
1
2
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B @aa:24, Rd
3
1
MOV.B Rs, @ERd
1
1
MOV.B Rs, @(d:16, ERd) 2
1
Rev. 3.00 Sep 27, 2006 page 729 of 872
REJ09B0325-0300