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HD64F3048VTF8 Datasheet, PDF (712/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip | |||
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Section 21 Electrical Characteristics
Table 21.16 Refresh Controller Bus Timing
Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VREF = 3.0 V to AVCC,
VSS = AVSS = 0 V, Ï = 2 MHz to 25 MHz, Ta = â20°C to +75°C (regular
specifications), Ta = â40°C to +85°C (wide-range specifications)
Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VREF = 4.5 V to AVCC,
VSS = AVSS = 0 V, Ï = 2 MHz to 25 MHz, Ta = â20°C to +75°C (regular
specifications), Ta = â40°C to +85°C (wide-range specifications)
Condition A
25 MHz
Item
RAS delay time 1*1
RAS delay time 2*1
RAS delay time 3*1
Row address hold time
RAS precharge time*1
CAS to RAS precharge
time*1 *2
CAS pulse width*2
RAS access time*1
Address access time
CAS access time*2
Write data setup time 3
CAS setup time*2
Read strobe delay time
Signal rise time (all input
pins except EXTAL)
Symbol
tRAD1
tRAD2
tRAD3
tRAH
tRP
tCRP
Min
â
â
â
0.5tcyc â5
1.0tcyc â15
1.0tcyc â15
Max
20
20
20
â
â
â
tCAS
tRAC
tAA
tCAC
tWDS3
tCSR
tRSD
tSR
1.0tcyc â18
â
â
â
1.0tcyc â25
0.5tcyc â15
â
â
â
2.0tcyc â35
1.5tcyc â40
1.0tcyc â30
â
â
25
100
Signal fall time (all input tSF
â
100
pins except EXTAL)
Notes: 1. The RAS pin is assigned to the CS3 pin.
2. The CAS pin is assigned to the RD pin.
Condition B
25 MHz
Min
Max
â
18
â
18
â
18
0.5tcyc â5 â
1.0tcyc â15 â
1.0tcyc â15 â
Test
Unit Conditions
ns Figure 21.10
to
Figure 21.16
1.0tcyc â18
â
â
â
1.0tcyc â25
0.5tcyc â15
â
â
2.0tcyc â35
1.5tcyc â40
1.0tcyc â30
â
â
25
â
100
ns
Figure 21.18
â
100
Rev. 3.00 Sep 27, 2006 page 684 of 872
REJ09B0325-0300
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